The invention deals in general with the field of power electronics. More particularly, the invention relates to an electronic power module having a 3D architecture for arranging electronic power switching chips. The invention further relates to electrical power converters, such as inverters.
Electronic power circuits are present in numerous fields of activity and, in particular, in the field of transport. In the last few decades, converters and electronic power modules have undergone considerable development, in particular in electric rail traction. With the desired energy switchover toward renewable energy sources that produce fewer CO2 emissions, there is a need for power electronics to be generalized even further and to meet increasing economic and technological constraints. In the field of transport, the automotive industry is subject to very restrictive emission and pollution discharge standards, which are leading to a real technological shift, with electrification of vehicles through hybrid or fully electrical architectures. Hybridization of airplane engines is also on the agenda for reducing CO2 emissions.
Conventionally, power modules are constructed with a planar arrangement of the electronic chips. In this planar arrangement, the rear faces of the chips are fixed to a substrate, and interconnection wires, known as bonding wires, are used to establish electrical connections on the front faces of the chips. The substrate, for example in the form of a ceramic lined with copper plates, performs a thermal interface function with a cooling device and an electrical insulation function.
This traditional planar architecture is not optimized in terms of compactness and cost, and has other drawbacks. The cooling of the chips only occurs through one of the faces thereof. The parasitic inductances, introduced in particular by the bonding wires and the electrical connecting tapes, generate overvoltages that increase the heat released and are potentially destructive. Moreover, the parasitic inductances conflict with higher switching frequencies, but these are favorable for compactness, in particular in power converters.
The 3D stacking of the chips is a promising path for improving the compactness of power modules and reducing parasitic inductances. An increased level of integration is generally also favorable for reducing costs. On the other hand, the 3D architecture accentuates the thermal constraints on the components.
US20160005675A1 discloses a power module having a 3D architecture. This power module 100 is shown herein in FIG. 1. The module 100 is cooled through the high-side and low-side faces thereof. The high-side and low-side faces comprise high-side and low-side heat sinks, 106 and 110, respectively. The 3D stack of the module 100 comprises a high-side electronic chip 220, a low-side electronic chip 210 and an interconnecting intermediate substrate 212 sandwiched between the chips 220 and 210. The chips 220 and 210 are soldered to the heat sinks 106 and 110, respectively, via one of the faces thereof and to the interconnecting intermediate substrate 212 via another of the faces thereof. An overmolding resin 108 provides tightness and mechanical cohesion of the module. The interconnecting intermediate substrate 212 is in this case a type of DCB (direct copper bond) or DBA (direct bonded aluminum) that comprises a central dielectric plate 224 lined on both sides with metal layers 216 and 217 of copper (DCB) or aluminum (DBA). The dielectric central plate 224 is a ceramic or a polyimide such as Kapton (registered mark).
The 3D stack implemented in the prior art power module 100 makes higher compactness possible. However, the electronic chips 210 and 220 are only cooled through a single face. An arrangement of this type may be found to be insufficient to guarantee high reliability at high power, at acceptable costs, by keeping the junction temperatures of the electronic chips below critical values.